Tutorial Sessions

Comprehensive workshops and hands-on tutorials across four specialized tracks

August 7, 2025 (Day 1)

7th August 2025 (Day 1)

Time Slot	System Track	Analog Track	Digital Track	Device Track
9:00 AM - 10:30 AM	Building RISC-V based System on Chips – Embedded to AI Enabled SoCs 90 mins	Testing & characterization of data converters 90 mins	Metric Driven Verification of a typical Low Power Mixed Signal (LPMS) SoC 90 mins	Foundry Compliance and Tapeout Qualification of Analog, Digital, and Mixed-Signal IC Designs for SCL 180nm CMOS Technology Node 90 mins
10:30 AM - 11:00 AM	☕Tea Break
11:00 AM - 12:30 PM	Building RISC-V based System on Chips – Embedded to AI Enabled SoCs (Continued) 90 mins	Testing & characterization of data converters (Continued) 90 mins	Workshop on Accelerating System Design: HDL Code Generation and Verification Techniques 90 mins	Foundry Compliance and Tapeout Qualification of Analog, Digital, and Mixed-Signal IC Designs for SCL 180nm CMOS Technology Node (Continued) 90 mins
12:30 PM - 2:00 PM	🍽️Lunch Break
2:00 PM - 3:30 PM	Google's Tensor Processing Unit: Understanding State-of-the-art AI Accelerator 90 mins	CMOS ANALOG DESIGN 90 mins	No session scheduled	NQS High-frequency Modeling of the Non-planar devices 90 mins
3:30 PM - 4:00 PM	☕Tea Break
4:00 PM - 5:30 PM	Design of a Battery-less Wireless Sensor Node Powered by RF Energy Harvester 90 mins	Neuromorphic Sensors: Architectures, IC Design Techniques, and Emerging Applications 90 mins	No session scheduled	Reliability-Aware Journey from FinFET to Stacked transistor 90 mins

Interactive Schedule:Click on any session title to view detailed information

All sessions are subject to change • Last updated: July 2025