Foundry Compliance and Tapeout Qualification of Analog, Digital, and Mixed-Signal IC Designs for SCL 180nm CMOS Technology Node

ChipIN Centre under Chips to Startup (C2S) Programme was set up at C-DAC Bangalore by Ministry of Electronics and Information Technology (MeitY), Government of India, to catalyze chip designing in India by catering to fabless chip design ecosystem in the country. The facility provides Multi-Project Wafer (MPW) support to Academic Institutions, Startups and MSMEs by enabling access to SCL foundry and overseas foundries. It provides centralized EDA Design Tools (Synopsys, Cadence, and Siemens-EDA, Xilinx, Ansys, Keysight, Silvaco) for IC design flow. The facility also provides design services like Fab compliance checks, validation, integration of designs, coordinating with identified firm for packaging of fabricated chips and enabling characterization and prototyping in a centralized manner. A significant component of this effort is exposing Academia, Govt. R&D organizations, and Startups/MSMEs to the entire VLSI Design flow necessary to have their designs ready for fabrication at SCL Foundry.