Building RISC-V based System on Chips (SoC) – Embedded to AI Enabled SoCs

The open-source RISC-V Instruction Set Architecture (ISA) is revolutionizing system-on-chip (SoC) design by enabling scalable, customizable, and cost-effective solutions for a wide range of applications, from low-power embedded systems to high-performance AI edge processors. Unlike proprietary ISAs, RISC-V's open ecosystem fosters innovation, allowing designers to tailor hardware to specific workloads without licensing barriers. This full-day, hands-on tutorial offers a comprehensive, step-by-step guide to designing, verifying, and prototyping RISC-V-based SoCs. It equips attendees with a systematic methodology to build application-specific SoCs, covering core selection, ISA customization, peripheral integration, AI accelerator interfacing, and FPGA prototyping. The session is designed for VLSI designers, embedded system engineers, and AI hardware developers seeking practical skills to leverage RISC-V in real-world projects. The tutorial begins with an in-depth overview of the RISC-V ISA, highlighting its modularity and extensibility. Participants will explore how RISC-V supports diverse applications, from resource-constrained embedded systems to compute-intensive tasks like AI inference and cryptographic processing. The session will guide attendees through the process of selecting appropriate RISC-V cores (e.g., RV32I, RV64G) based on performance, power, and area constraints. It will also cover techniques for customizing or extending the ISA to meet domain-specific requirements, such as adding custom instructions for signal processing or machine learning workloads. Practical examples will demonstrate how to balance design trade-offs while ensuring compatibility with the RISC-V ecosystem. Next, the tutorial delves into SoC architecture design, focusing on the integration of RISC-V cores with on-chip components. Attendees will learn to implement efficient interconnects using industry-standard bus protocols like AXI4 and AHB, ensuring seamless communication between processor cores, memory subsystems, and peripherals. The session will cover memory mapping strategies to optimize data flow and minimize latency, alongside the integration of standard peripherals such as UART, SPI, I2C, and GPIO. Real-world design considerations, such as power management and clock domain crossing, will be addressed to provide a holistic view of SoC development. A key focus of the tutorial is enabling AI functionality in RISC-V-based SoCs. Participants will learn how to interface RISC-V cores with custom hardware blocks, such as multiply-accumulate (MAC) arrays, vector processing units, and dedicated AI accelerators. The session will explore the use of standard bus interfaces for integrating these components, alongside techniques like direct memory access (DMA) for efficient data transfers. Topics such as co-simulation for hardware-software validation, real-time task scheduling for AI workloads, and optimization of compute pipelines will be discussed. Practical examples will illustrate how to achieve high throughput and low latency for AI applications at the edge. The final segment of the tutorial focuses on verification, simulation, and prototyping of RISC-V-based SoCs. Attendees will gain hands-on experience with ASIC design tools for simulation and synthesis, learning how to verify SoC functionality and performance. The session will cover FPGA prototyping on platforms like Xilinx or Intel boards, enabling participants to test their designs in hardware. Techniques for benchmarking and profiling SoCs at the hardware level will be demonstrated, with a focus on metrics like power consumption, throughput, and latency. Applications ranging from embedded control systems to AI inference will be showcased to highlight the versatility of RISC-V SoCs. This tutorial is highly practical, supported by example projects, simulation outputs, and reusable scripts that attendees can adapt for their own designs post-symposium. Hands-on exercises will reinforce key concepts, allowing participants to experiment with RISC-V core configurations, peripheral integration, and AI accelerator interfacing. By the end of the session, attendees will be equipped to design, verify, and prototype their own RISC-V-based SoCs, bridging the gap between theoretical concepts and real-world implementation. This tutorial is ideal for professionals and researchers aiming to harness the power of RISC-V for next-generation SoC development.