NQS High-frequency Modeling of the Non planar devices

The continuous scaling of semiconductor devices has driven the technology industry to develop faster, smaller, and more efficient transistors. As technology nodes have miniaturized, traditional planar transistors have struggled with short-channel effects, leakage currents, and power consumption issues. FinFETs emerged as a revolutionary solution to address these challenges. The FinFET structure, with its three-dimensional design, offers superior electrostatic control by wrapping the gate around a vertical fin. FinFETs have significantly enhanced transistor performance by improving electrostatic control and enabling continued scaling. Despite its advantages, below the sub-22nm node, FinFETs possess challenges, such as parasitic capacitance and resistance, fin depopulation, and variability in fin height and width. Additionally, the fixed height of fins constrains area scaling, creating a need for further innovations in transistor design. In particular, as transistor architectures become more complex, accurate capacitive and resistive behavior modeling becomes critical for device circuit co design. For FinFETs, modeling the gate capacitance and resistive paths is relatively straightforward. However, stacked transistor architectures introduce new complexities due to the vertical arrangement of channels and gates. These vertical stacks create capacitive coupling between the layers, which impacts device performance, particularly in high-frequency applications. Nanosheet transistors offer improved high-frequency performance due to reduced parasitic capacitance and improved electrostatic control. Accurate modeling of Nanosheet transistors in high-frequency and their circuit implications are critical for leveraging their potential in modern technology nodes to ensure signal integrity. Thus, designing a robust model (quasi-static or non-quasi static), addressing the SOEs, and evaluating the reliability challenges requires proper attention in agreeing to accept such stacked transistors as an integrated industrial fit. In addition, the radiation effects, particularly in advanced nodes where devices are more sensitive to external perturbations, also impact the resistive paths within the transistor. High-energy particles can induce transient faults or cause permanent resistance changes, necessitating robust radiation-aware resistance models for mission-critical applications. To navigate these complexities, modern Technology Computer-Aided Design (TCAD) tools are increasingly being augmented with Machine Learning (ML) techniques. ML-driven TCAD can accelerate device simulation, optimize fabrication parameters, and predict degradation pathways with greater accuracy. These data-driven approaches enable the exploration of large design spaces and support more robust modeling of electrical behavior and reliability concerns. This tutorial session will provide a detailed overview of the evolution from FinFETs to advanced stacked architectures, emphasizing their implications for high-frequency performance, modeling complexity, and reliability challenges. Through the lens of both traditional and ML-augmented TCAD approaches, we aim to explore the design considerations and circuit-level impacts that will define the next era of semiconductor innovation.