Reliability-Aware Journey from FinFET to Stacked transistor

The continuous scaling of semiconductor devices has driven the technology industry to develop faster, smaller, and more efficient transistors. As technology nodes have miniaturized, traditional planar transistors have struggled with short-channel effects, leakage currents, and power consumption issues. FinFETs emerged as a revolutionary solution to address these challenges. The FinFET structure, with its three-dimensional design, offers superior electrostatic control by wrapping the gate around a vertical fin. FinFETs have significantly enhanced transistor performance by improving electrostatic control and enabling continued scaling. Despite its advantages, below the sub-22nm node, FinFETs possess challenges, such as parasitic capacitance and resistance, fin depopulation, and variability in fin height and width. Additionally, the fixed height of fins constrains area scaling, creating a need for further innovations in transistor design. These limitations have prompted the development of new transistor architectures, such as stacked transistors, including Nanosheet FET, Forksheet FET, and CFET (Complementary FET), with improved power, performance, area, and cost (PPAC). These architectures comprise vertically stacked multiple channels/sheets, reducing the device's overall footprint while maintaining or improving performance. Stacked devices offer enhanced flexibility in gate control and channel width optimization and improve power efficiency since multiple channels are integrated without increasing the device's lateral area, enabling more transistors to be packed into a smaller space. The integrity of the device (e.g., stacked transistor) raises several call-up challenges related to the electrical and thermal reliability. The vertical stacking of channels in these devices creates complex electrostatic interactions between sheets, leading to research on performance optimization. Further, owing to the compact stacked design, the channels/sheets are prone to self-heating problems, as the heat accumulates in the wrapped channel by low-thermal-conductivity material. Further, the heat generated in one sheet may couple to another, affecting the device's normal operation. Therefore, the mutual coupling of electrical and thermal parameters is essentially considered for such stacked transistors. Electrical coupling, in one way or another, can increase parasitic capacitance and interfere with channel signal transmission, leading to degraded device performance. On the other hand, the mutual electrical and thermal coupling exacerbates self-heating issues, negatively affecting both performance and reliability. Furthermore, the additional internal and external process variations, such as interface traps, random dopant fluctuation (RDF), gate metal grain granularities (MGG), line-edge roughness (LER), NBTI, etc., raise reliability concerns, which play a critical role, leading to premature device degradation and failure. Ensuring the long-term reliability of stacked transistors requires careful consideration of these failure mechanisms and the development of mitigation strategies, which can help predict device aging. This tutorial session will provide a detailed overview of the evolution from FinFETs to advanced stacked architectures, emphasizing their implications for high-frequency performance, modeling complexity, and reliability challenges. Through the lens of both traditional and ML-augmented TCAD approaches, we aim to explore the design considerations and circuit-level impacts that will define the next era of semiconductor innovation.