Workshop on Accelerating System Design: HDL Code Generation and Verification Techniques

In the rapidly evolving landscape of digital system design, engineers and researchers face increasing demands for faster development cycles, higher design reliability, and efficient deployment of complex algorithms onto hardware platforms. Traditional hardware design flows—often reliant on manual Hardware Description Language (HDL) coding and labour-intensive verification—can be time-consuming and error-prone, ultimately slowing innovation and prolonging time-to-market. To address these challenges, this comprehensive tutorial aims to equip participants with modern, model-based workflows that leverage the power of MATLAB and Simulink for streamlined HDL code generation and robust verification. The workshop demonstrates how system architects and engineers can move efficiently from conceptual algorithms to verified, synthesizable hardware designs, highlighting the use of HDL Coder and HDL Verifier—two industry-standard tools from MathWorks that facilitate automatic HDL code generation and comprehensive verification. This tutorial is designed for engineers, researchers, and students involved in FPGA, ASIC, or SoC design who wish to accelerate the design process by automating code generation from high-level models, ensure design correctness through systematic verification techniques, reduce human error inherent in manual HDL development, and achieve faster time-to-market for innovative products.