Domain
This falls at the intersection of computer architecture and artificial intelligence.
Prerequisites
Basic knowledge of Analog and Mixed Signal blocks is required. Knowledge of Low Power Concepts are good.
Key Words
Abstract
The complexity of Low Power Mixed Signal Systems-on-Chip (SoCs) demands a verification strategy that integrates expertise from multiple domains, including analog, digital, verification methodology, and low power design. To meet time- to-market challenges, a well-planned verification architecture is crucial. This tutorial presents a comprehensive methodology for verification of Low Power Mixed Signal SoCs, focusing on achieving complete coverage with minimal simulation and debug time. The approach to be covered in thistutorial emphasizes automation, parallel development cycles, and optimized simulation performance, ensuring faster identification and closure of critical design issues. By providing clear debug guidelines and streamlining the verification process, the methodology reduces the number of iterations required for block and sub-block verification, ultimately accelerating the overall verification efficiency and time-to-market for Low Power Mixed Signal SoCs. A sample Low Power Mixed Signal Systems-on-Chip will be used to describe an efficient metric driven. In this tutorial, I will discuss the real time challenges and possible solutions during LPMS SoC verification. The tutorial will cover different aspects mainly categorized as: • Writing Power Intent for LPMS SoC using IEEE 1801 UPF. • Define domain conversion elements to cater Multi Supply. • Integrating Analog IP in SoC Design • Setting Up the UVM Testbench with different Power Modes of SoC • Handling multiple issues during verification including incorrect supply, unwanted X-State, Low Power Boundary issues, Analog solver convergence issues, performance and integration challenge. The LPMS SoC used in tutorial will be like modern time SoCs like micro- controllers and other SoC used in automotive and industrial applications. After attending the tutorial, audience will learn a modern time metric driven methodology used by a seasoned verification architect to reduce debug and verification time.
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